I dont know on this one, i have never messed with these settings before so I dont have an answer, sorry bud.
It has to do at the hardware level and it would be best to find out how the L2 is done on the chip. Instead of 1 8 MB like it is doing with l# it is doing 4 at 2 MB each, so that means there is 4 2MB locations on the chip, so most likly 2 cores get 1. 8 cores then 4 of the 2 MB.
So 2 cores have used up 1 of the 2MB while the other cores still have their own. But I am only going by a fraction of information and I may be totally wrong, trying to look up info on them isnt pulling up much lol
Shane